منابع مشابه
Profile-Driven Instruction Level Parallel Scheduling
VLIW scheduling, profile driven scheduling, superblocks, hyperblocks Code scheduling to exploit instruction level parallelism (lLP) is a central problem in compiler optimization research, in light of the increased use of long-instruction-word computers. Unfortunately, optimum scheduling is computationally intractable, and one must resort to carefully crafted heuristics in practice. If the scope...
متن کاملInstruction Scheduling for Instruction Level Parallel Processors
Nearly all personal computer and workstation processors, and virtually all high-performance embedded processor cores, now embody instruction level parallel (ILP) processing in the form of superscalar or very long instruction word (VLIW) architectures. ILP processors put much more of a burden on compilers; without “heroic” compiling techniques, most such processors fall far short of their perfor...
متن کاملComputer-assisted instruction.
THIS ARTICLE reports on a program designed to develop computer literacy by offering instruction in a wide range of programming languages. Beginning in 1968, a computer-assisted course in computer programming was conducted through the Business Department of Woodrow Wilson High School, an "inner city" school in the Hunter's Point-Bayview area of San Francisco. Each day for three semesters, betwee...
متن کاملNon-uniform Instruction Scheduling
Dynamic instruction scheduling logic is one of the most critical and cycle-limiting structures in modern superscalar processors, and it is not easily pipelined without significant losses in performance. However, these performance losses are incurred only due to a small fraction of instructions, which are intolerant to the non-atomic scheduling. We first perform an empirical analysis of the inst...
متن کاملPrecise Instruction Scheduling
Pipeline depths in high performance dynamically scheduled microprocessors are increasing steadily. In addition, level 1 caches are shrinking to meet latency constraints but more levels of cache are being added to mitigate this performance impact. Moreover, the growing schedule-toexecute-window of deeply pipelined processors has required the use of speculative scheduling techniques. When these e...
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ژورنال
عنوان ژورنال: International Journal of Parallel Programming
سال: 1994
ISSN: 0885-7458,1573-7640
DOI: 10.1007/bf02577873